This invention relates to programmable logic array integrated circuit devices, and more particularly to improvements in the ways in which interconnect lines are provided in such devices.
Programmable logic array integrated circuits are well known as shown, for example, by such references as Pedersen et al. U.S. Pat. No. 5,260,610 and Cliff et al. U.S. Pat. No. 5,260,611. As is exemplified by these references, many recent programmable logic array devices have a large number of logic regions disposed in a two-dimensional array on the integrated circuit. Each logic region is capable of performing a relatively simple logic function, the particular logic function performed by each region being selected when the device is "programmed" prior to its use as a logic device. Interconnection conductors are provided on the device for (1) delivering to each logic region the signals on which that logic region will operate, and (2) conveying from each logic region the signals indicative of the logic performed by that logic region. These interconnection conductors can be used to convey output signals from one logic region to the inputs of other logic regions, thereby making it possible for the logic array device to perform much more complex logic functions than any individual logic region can perform. Just as the logic functions performed by the individual logic regions are programmable, many of the connections between interconnection conductors and between the logic regions and the interconnection conductors are also typically programmable so that the manner in which signals are routed through the interconnection conductors and the manner in which the logic regions are thereby interconnected is also programmable.
It is extremely difficult to design a programmable logic array device of the type described above which has just the right ratio of logic region resources to interconnection conductor resources. These devices are intended as general-purpose devices, and the designer of a device cannot know all of the many uses to which customers may wish to put the device. For example, some uses may require a high degree of interconnection between logic regions, while other uses may need much less interconnection. Even the type of interconnection needed by the user may vary. Some uses may involve functions with large fan out, requiring wide distribution of a logic region output to many other logic regions. Other uses may involve more incremental logic, never requiring that any logic region output go to more than a small number of other logic regions.
Certain early, relatively small programmable logic array integrated circuit devices could include completely or almost completely general interconnection circuit resources, even though only a fraction of such resources was ever actually employed in any use of those devices. Such completely general interconnectivity becomes increasingly wasteful and ultimately prohibitive as the amount of logic on the device increases. Thus it becomes increasingly important to devise less than completely general interconnection resources which nevertheless allow the device to satisfy the maximum number of possible uses.
The disincentives to provide completely general interconnection capability on more sophisticated programmable logic array devices is especially strong in the case of reprogrammable devices. This is so because reprogrammable interconnection elements tend to be larger and to have greater circuit loading and signal delay characteristics than one-time-only programmable interconnection elements. Thus in the design of reprogrammable devices there is even greater pressure to economize on the number of interconnection elements provided to hold down overall device size and to reduce circuit loading and signal propagation delay. While it may be feasible to provide fully populated or at least quite densely populated regions of interconnection capability in some one-time-only programmable devices (e.g., those shown, for example, in El Gamal et al., "An Architecture for Electrically Configurable Gate Arrays," IEEE Journal of Solid-State Circuits, Vol. 24, No. 2, April 1989, pp. 394-98; El-Ayat et al., "A CMOS Electrically Configurable Gate Array," IEEE Journal of Solid-State Circuits, Vol. 24, No. 3, June 1989, pp. 752-62; and Elgamal et al. U.S. Pat. No. 4,758,745), such high density interconnection populations tend to be much more disadvantageous in reprogrammable devices, especially as the amount of logic on the device increases.
One approach to providing interconnection circuitry that will meet a variety of needs is shown in Freeman U.S. Pat. No. Re. 34,363. In the Freeman system many short lengths of conductor are programmably interconnectable to route signals from one logic region to one or more other logic regions. A disadvantage of this approach is that each conductor interconnection tends to delay and attenuate the signal being transmitted. Because the numbers of conductor interconnections through which various signals may have to travel can vary significantly, maintaining synchronization and uniform level among several signals can be difficult and/or may limit the speed at which the device can be operated. The above-mentioned El Gamal, El-Ayat, and Elgamal references show other examples of circuits in which multiple short lengths of conductor are programmably "pieced together" to make required longer conductors.
Another approach to providing flexible interconnection circuitry is shown in the above-mentioned Pedersen et al. patent. In this system, the logic regions are grouped into "logic array blocks" of 16 logic regions each. Several interconnection conductors are associated with each logic array block for providing interconnection among the logic regions in the block. In addition, global horizontal and global vertical conductors extend respectively along rows and columns of logic array blocks. The global horizontal conductors provide interconnection among the blocks in each row. The global vertical conductors provide interconnection among the rows of blocks. Thus two levels of conductor extent are provided: (1) local conductors spanning the 16 logic regions in each logic array block, and (2) global conductors spanning either rows or columns of logic array blocks. While this is an improvement over the Freeman system in the respect that it is not necessary to patch together large numbers of short conductors to provide required long interconnections, it can be wasteful of interconnection resources. For example, making a connection between two adjacent logic regions in a logic block consumes a local conductor which is longer than the necessary connection. Similarly, connecting horizontally adjacent logic blocks consumes a global horizontal conductor, which again is much longer than the necessary connection.
More recent products of the assignee of the above-mentioned Freeman patent have added longer, uninterrupted conductors, and also uninterrupted conductors between adjacent logic regions (see, for example, Carter U.S. Pat. No. 4,642,487). However, these products still rely heavily on piecing together many relatively short interconnection conductors to make certain kinds of interconnections. The above-mentioned El-Ayat reference mentions (in the sentence bridging pages 752 and 753) the use of conductor segments of progressively increasing length. Again, however, this architecture relies on piecing these conductors together to make longer connections when necessary.
In view of the foregoing it is an object of this invention to provide improved interconnection circuitry for programmable logic array devices.
It is another object of this invention to provide interconnection circuitry for programmable logic array devices which neither requires connecting large numbers of short conductor segments together to make long-distance connections, nor which requires the use of long conductors to make relatively short connections.